As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (FinFET). Similar to planar transistors, source and drain silicides may be formed on the source and drain regions of FinFETs. However, since the fins of FinFETs are typically narrow, current crowding may occur. In addition, it is difficult to land contact plugs onto the source/drain portions of fins. Epitaxy semiconductor layers are thus formed on the fins to increase their volumes using epitaxy processes. A typical FinFET is fabricated with a thin vertical “fin” (or fin structure) extending from a substrate formed by, for example, etching away a portion of a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. Having a gate on both sides of the channel allows gate control of the channel from both sides.
It was found that trained materials in recessed source/drain (S/D) portions of the FinFET utilizing selectively grown silicon germanium (SiGe) may enhance carrier mobility. The stress effects improve charge mobility through the channel, thereby improving device performance. However, there are challenges to implementation of such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, strained material volume is one of the key knobs to increase channel strain, and it is limited by fin critical dimension, fin profile and fin pitch. For device boosting, strained material volume is preferably as large as possible.
Accordingly, what are needed are an improved device and a method for fabricating a strained structure.